CDCM1802 Datasheet (Texas Instruments)

CDCM1802, Clock Buffer

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 and Y0, and one single-ended LVCMOS output, Y1.

It is specifically designed for driving 50-Ω transmission lines.

The LVCMOS output is delayed by 1.6 ns over the PECL output sta

CDCM1802 Features

* 1 Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output

* Programmable Output Divider for Both LVPECL and LVCMOS Outputs

* 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise

* 3.3-V