A3S28D40JTP 128M Double Data Rate Synchronous DRAM

Zentel

A3S28D40JTP Description

A3S28D40JTP 128M Double Data Rate Synchronous DRAM 128Mb DDR SDRAM Specification A3S28D40JTP Zentel Electronics Corp.Revision 1.0 Oct., 2013 A3S2.
A3S28D40JTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

A3S28D40JTP Features

* - VDD=VDDQ=2.5V+0.2V (-50) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on

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Datasheet Details

Part number: A3S28D40JTP
Manufacturer: Zentel
File Size: 533.07 KB
Datasheet: A3S28D40JTP-Zentel.pdf
Description: 128M Double Data Rate Synchronous DRAM

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128M Double Data Rate Synchronous DRAM Zentel

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