Description
DQ0-31 A0-22 WE#1-2 CS#1-2 OE# RESET# WP#/ACC RY/BY# VCC VIO GND DNU NC Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Hardware Reset Hardware Write Protection/Acceleration Ready/Busy Output Power Supply I/O Power Supply Ground Do Not Use Not Connected
GND
DQ25
WE2#
VIO
NC
DNU
NC
VCC
VIO
VCC
DQ17
DQ27
DQ29
DQ31
NC
NC
NC
NC
VCC
VIO
DQ24
DQ19
DQ21
DQ23
NC
NC
NC
NC
VIO
VCC
DQ16
DQ26
DQ28
DQ30
NC
NC
NC
NC
VCC
GND
CS2#
DQ18
DQ20
Features
- Access Times of 70, 90, 100, 120ns Packaging.
- 159 PBGA, 13x22mm.
- 1.27mm pitch 1,000,000 Erase/Program Cycles per sector Page Mode.
- Page size is 8 words: Fast page read access from random locations within the page. Sector Architecture.
- Bank A (16Mb): 4Kw x 8 and 32 Kw x 31.
- Bank B (48Mb): 32Kw x 96.
- Bank C (48Mb): 32Kw x 96.
- Bank D (16Mb): 4Kw x 8 and 3Kw x 31 Both top and bottom boot blocks Zero Power Operation Organized as 8Mx32, us.