Si5383 Datasheet (Silicon Laboratories) - Network Synchronizer Clocks Supporting

Si5383, Network Synchronizer Clocks Supporting

4 3.1 Standards Compliance .

4 3.2 Frequency Configuration .

4 3.3 DSPLL Loop Bandwidth in Standard Input Mode .

Si5383/84 Rev D Data Sheet Network Synchronizer Clocks Supporting 1 PPS to 750 MHz Inputs The Si5383/84 combines the industry’s smallest footprint and lowest power network synchronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter.

The Si5383/84 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless communications systems, and data center switches requiring both traditional and packet based network synchronization.

The three independent DSPL

Si5383 Features

* One or three independent DSPLLs in a single monolithic IC supporting flexible SyncE/IEEE 1588 and SETS architectures

* Input frequency range:

* External crystal: 25-54 MHz

* REF clock: 5-250 MHz

* Diff clock: 8 kHz - 750 MHz

* LVCMOS clock: 1 PPS, 8