Description
PC66 4M x 64 2 bank SDRAM module PC66 4M x 72 2 bank SDRAM module Module Height 1,15“ 1,15“
Pin Names
A0-A10 BS (A11) DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0, CKE1 CLK0 - CLK3 DQMB0 - DQMB7 CS0 - CS3 Vcc Vss SCL SDA N.C.Address Inputs( RA0 ~ RA10 / CA0 ~ CA8) Bank Select Data Input/Output Check Bits (x72 organisation only) Row Address Strobe Column Address Strobe Read / Write Input Clock Enable Clock Input Data Mask Chip Select Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for
Features
- s are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’ s) are stable during tRC(min. ). 3. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto.