HYS64V2100G - 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module

Siemens

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Datasheet Details

Part number	HYS64V2100G
Manufacturer	Siemens
File Size	75.48 KB
Description	3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module
Datasheet	HYS64V2100G_SiemensSemiconductorGroup.pdf

HYS64V2100G Product details

Description

PC66 2M x 64 SDRAM module PC66 2M x 72 SDRAM module PC66 2M x 64 SDRAM COB module PC66 2M x 72 SDRAM COB module Pin Names A0-A10 A11 (BS) DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0 Address Inputs( RA0 ~ RA10 / CA0 ~ CA8) Bank Select Data Input/Output Check Bits (x72 organisation only) Row Address Strobe Column Address Strobe Read / Write Input Clock Enable CLK0, CLK1 DQMB0 DQMB7 CS0 - CS3 Vcc Vss SCL SDA N.C.Clock Input Data Mask Chip Select Power (+3.3 Volt) Ground Clock for Presence Detect Serial D

Features

d after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have V il = 0.4 V and V ih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V ih and Vil. All AC meas.

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Other Datasheets by Siemens

HYS64V2100GCU-10 - 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module
HYS64V2100GU-10 - 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module
HYS64V2200GU-10 - 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
HYS64V2200GU-8 - 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
HYS64V2200GU-8-3 - 3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module
HYS64V1000GS-10 - 3.3V 1M x 64-Bit SDRAM Module 3.3V 1M x 72-Bit SDRAM Module

Published: Apr 23, 2005 |