M6MGT321S8TP Datasheet - Renesas

M6MGT321S8TP, CMOS SRAM

www.DataSheet4U.com Renesas LSIs M6MGB/T321S8TP 33,554,432-BIT (2,097,152 - WORD BY 16-BIT/4,194,304-WORD BY 8-BIT) CMOS 3.0V-ONLY FLASH MEMORY & 8,

Features

* DINOR (Divided bit-line NOR) architecture for the memory cell. Access Time Flash 85ns (Max. ) 8M-bit SRAM is a 1,048,576 bytes / 524,288 words SRAM 85ns (Max. ) asynchronous SRAM fabricated by silicon-gate CMOS technology. Supply Voltage VCC=2.7 ~ 3.0V The M6MGB/T321S8TP is a Stacked micro Multi Chip

M6MGT321S8TP_Renesas.pdf