ISLA212P50 - 500MSPS ADC

Renesas

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Datasheet Details

Part number	ISLA212P50
Manufacturer	Renesas
File Size	1.82 MB
Description	500MSPS ADC
Datasheet	ISLA212P50-Renesas.pdf

ISLA212P50 Product details

Description

- 72 Ld QFN, LVDS Mode PIN NUMBER 1, 2, 17, 57, 58, 59, 60 6, 13, 19, 20, 21, 70, 71, 72 5, 7, 12, 14 27, 32, 62 26, 45, 61, 65 3 4 8, 9 LVDS PIN NAME DNC AVDD AVSS OVDD OVSS NAPSLP VCM VINN LVDS PIN FUNCTION Do Not Connect 1.8V Analog Supply Analog Ground 1.8V Output Supply Output Ground Tri-Level Power Control (Nap, Sleep modes) Common Mode Output Analog Input Negative FN7843 Rev 2.00 January 25, 2013 Page 2 of 38 ISLA212P50 Pin Descriptions - 72 Ld QFN, LVDS Mode (Continued) PIN NUMB

Features

Automatic fine interleave correction calibration.
Single supply 1.8V operation.
Clock duty cycle stabilizer.
75f clock jitter.
700MHz bandwidth.
Programmable built-in test patterns.
Multi-ADC support - SPI programmable fine gain and offset control - Support for multiple ADC synchronization - Optimized output timing.
Nap and sleep modes - 200µs sleep wake-up time.
Data output clock.
DDR LVDS-compatible or L.

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Published: May 30, 2020 |