HD74HC78 - Dual J-K Flip-Flops

Renesas

Datasheet Details

This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse.

High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 pF).
High Output Current: Fanout of 10 LSTTL Loads.
Wide Operating Voltage: VCC = 2 to 6 V.
Low Input Current: 1 µA max.
Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C).
Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74HC78FPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP HD74HC78RPEL SOP-14 pin (JEDEC) PR.

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Published: Apr 4, 2016 |