8V79S683 Datasheet (Renesas) - JESD204B/C Compliant Fanout Buffer and Divider

8V79S683, JESD204B/C Compliant Fanout Buffer and Divider

The 8V79S683 is a fully integrated, clock and SYSREF signal fanout buffer for JESD204B/C applications.

It is designed as a high-performance clock and converter synchronization solution for wireless base station radio equipment boards with JESD204B/C subclass 0, 1, and 2 compliance.

The main function

8V79S683 Features

* ▪ Distribution, fanout, phase-delay of clock and SYSREF signals ▪ Very low output noise floor: -158.8dBc/Hz noise floor (245.76MHz) ▪ Supports clock frequencies up to 3GHz, including clock output frequencies of 983.04MHz, 491.52MHz, 245.76MHz, and 122.88MHz ▪ Four output channels with a total of 16