8T74S208A-01 Datasheet (Renesas) - LVDS Clock Divider and Fanout Buffer

8T74S208A-01, LVDS Clock Divider and Fanout Buffer

The 8T74S208A-01 is a high-performance differential LVDS clock divider and fanout buffer.

The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks.

The 8T74S208A-01 is characterized to operate from a 2.5V power supply.

Guaranteed output-to-output

8T74S208A-01 Features

* One differential input reference clock Differential pair can accept the following differential input levels: LVDS, LVPECL, CML Integrated input termination resistors Eight LVDS outputs Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8 Maximum input clock frequency: 1GHz LVCMOS interface level