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8T74S208A-01 LVDS Clock Divider and Fanout Buffer

8T74S208A-01 Description

2.5V Differential LVDS Clock Divider and Fanout Buffer 8T74S208A-01 REFER TO PCN# N1608-01, Effective Date November 18, 2016 FOR NEW DESIGNS USE PAR.
The 8T74S208A-01 is a high-performance differential LVDS clock divider and fanout buffer.

8T74S208A-01 Features

* One differential input reference clock Differential pair can accept the following differential input levels: LVDS, LVPECL, CML Integrated input termination resistors Eight LVDS outputs Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8 Maximum input clock frequency: 1GHz LVCMOS interface level

8T74S208A-01 Applications

* demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the reference source easy and reduce passive component count. Each output can be individually enabled or disabled in the high-impedance state controlled by a I2C register. On power-up

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