8T74S208B Datasheet (Renesas) - LVDS Clock Divider and Fanout Buffer

8T74S208B, LVDS Clock Divider and Fanout Buffer

The 8T74S208B is a high-performance differential LVDS clock divider and fanout buffer.

The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks.

The 8T74S208B is characterized to operate from a 2.5V power supply.

Guaranteed output-to-output and pa

8T74S208B Features

* One differential input reference clock

* Differential pair can accept the following differential input levels: LVDS, LVPECL, CML

* Integrated input termination resistors

* Eight LVDS outputs

* Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8