Datasheet Specifications
- Part number
- 8SLVD1212
- Manufacturer
- Renesas ↗
- File Size
- 2.06 MB
- Datasheet
- 8SLVD1212-Renesas.pdf
- Description
- LVDS fanout buffer
Description
1:12, LVDS Output Fanout 8SLVD1212 Datasheet .
Features
* ▪ Twelve low skew, low additive jitter LVDS output pairs ▪ Two selectable, differential clock input pairs ▪ Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL, CML ▪ Maximum input clock frequency: 2GHz (maximum) ▪ LVCMOS/LVTTL interface levels for the conApplications
* that demand well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The 8SLVD1212 is optimized for low power consumption and8SLVD1212 Distributors
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