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8SLVD1204-33 - LVDS Output Fanout Buffer

General Description

The 8SLVD1204-33 is a high-performance differential LVDS fanout buffer.

The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals.

The 8SLVD1204-33 is characterized to operate from a 3.3V power supply.

Key Features

  • Four low skew, low additive jitter LVDS output pairs.
  • Two selectable differential clock input pairs.
  • Differential PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL.
  • Maximum input clock frequency: 2GHz.
  • LVCMOS/LVTTL interface levels for the control input select pin.
  • Output skew: 20ps (maximum).
  • Propagation delay: 310ps (maximum).
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Datasheet Details

Part number 8SLVD1204-33
Manufacturer IDT
File Size 513.19 KB
Description LVDS Output Fanout Buffer
Datasheet download datasheet 8SLVD1204-33 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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2:4, LVDS Output Fanout Buffer 8SLVD1204-33 DATASHEET Description The 8SLVD1204-33 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1204-33 is characterized to operate from a 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD1204-33 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.