8SLVD1212 Datasheet PDF - Renesas LVDS fanout buffer Specs

8SLVD1212 - LVDS fanout buffer

Datasheet Summary

Description

The 8SLVD1212 is a high-performance differential LVDS fanout buffer.

The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals.

The 8SLVD1212 is characterized to operate from a 2.5V power supply.

Features

Twelve low skew, low additive jitter LVDS output pairs.
Two selectable, differential clock input pairs.
Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL, CML.
Maximum input clock frequency: 2GHz (maximum).
LVCMOS/LVTTL interface levels for the control input select pins.
Output skew: 40ps (maximum).
Propagation delay: 310ps (typical).
Low additive phase jitter, RMS; fREF = 156.25MHz, 10kHz to 20MHz: 77fs (typi.

Datasheet Details

Part number	8SLVD1212
Manufacturer	Renesas
File Size	2.06 MB
Description	LVDS fanout buffer
Datasheet	8SLVD1212 Datasheet
Additional preview pages of the 8SLVD1212 datasheet.

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Full PDF Text Transcription

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1:12, LVDS Output Fanout 8SLVD1212 Datasheet Description The 8SLVD1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1212 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the device ideal for clock distribution applications that demand well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The 8SLVD1212 is optimized for low power consumption and low additive phase noise.

Published: Sep 26, 2023 |