Description
COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F598N N74F598D PKG DWG #
DESCRIPTION
The 74F598 consists of an 8
bit storage register feeding a parallel
in/serial
in, parallel
out/serial
out 8
bit shift register.
triggered clocks.
pin plastic DIP 20
pin plastic
Features
- High impedance PNP base input for reduced loading (20µA in High and Low states).
- 8.
- bit parallel storage register.
- Shift register has asynchronous direct overriding reset.
- Shift load SHLD is functional when SHCP is Low and locked out when SHCP is High.
- Guaranteed shift frequency DC to 105MHz.
- Parallel 3.
- State I/O storage register inputs and shift register parallel outputs
The shift register load function has been modified to.
74F598_PhilipsSemiconductors.pdf
