NB6L56 - 2.5V / 3.3V Dual 2:1 Differential Clock / Data Multiplexer

ON Semiconductor

NB6L56 Datasheet Preview — Preview of NB6L56 PDF

Datasheet Details

Part number	NB6L56
Manufacturer	ON Semiconductor ↗
File Size	134.48 KB
Description	2.5V / 3.3V Dual 2:1 Differential Clock / Data Multiplexer
Datasheet	NB6L56-ONSemiconductor.pdf

NB6L56 Product details

Description

Pin Name I/O Pin Description 1, 4 5, 8 25, 28 29, 32 INB0, INB0 INB1, INB1 INA0, INA0 INA1, INA1 LVPECL, CML, LVDS Input Noninverted, Inverted Differential Input pairs (Note 1).Default state is indeterminate if left floating open.Do not connect unused input pairs with one input connected to VCC and the complementary input to GND.For differential and single ended interface, see “Interface Applications”.2, 6 26, 30 VTB0, VTB1 VTA0, VTA1 Internal 100 W Center tapped Termination

Features

Maximum Input Data Rate > 2.5 Gbps.
Maximum Input Clock Frequency > 2.5 GHz.
Jitter < 1 ps RMS RJ (Data) < 10 ps PP DJ (Data) < 0.7 ps RMS Crosstalk induced jitter (CLOCK).
360 ps Max Propagation Delay.
180 ps Max Rise and Fall Times.
Operating Range: VCC = 2.5 ± 5% (2.375 V to 2.625 V) VCC =3.3 ± 10% (3.0 V to 3.6 V).
Internal 50 W Input Termination Resistors.
Industrial Temp. Range (.
40°C to 85°C).
QFN.

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Other Datasheets by ON Semiconductor

NB6L572M - 2.5V / 3.3V Differential 4:1 Mux To 1:2 CML Clock/Data Fanout / Translator
NB6L11 - 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL
NB6L11M - Differential CML Fanout Buffer
NB6L11S - Input to LVDS Fanout Buffer/Translator
NB6L14 - Differential 1:4 LVPECL Fanout Buffer
NB6L14M - Differential 1:4 CML Fanout Buffer

Published: Sep 1, 2015 |