MC100LVEL14 - 1:5 Clock Distribution Chip

Description

designed explicitly for low skew clock distribution applications.

The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal.

Features

• a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as ca.