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MC100LVEL14 - 1:5 Clock Distribution Chip

Key Features

  • a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or le.

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Full PDF Text Transcription for MC100LVEL14 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for MC100LVEL14. For precise diagrams, and layout, please refer to the original PDF.

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 1:5 Clock Distribution Chip The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock d...

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w 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of –3.0V to –3.8V ( or 3.0V to 3.8V). If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor.

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ON Semiconductor Logo MC100LVEL14 1:5 Clock Distribution Chip ON Semiconductor

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