74LS174 Datasheet (ON Semiconductor)

74LS174, LOW POWER SCHOTTKY

The LS174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs.

The Clock (CP) and Master Reset (MR) are common to all flip-flops.

Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW to HIGH Clock (CP) transition.

A LOW input

SN74LS174 Hex D Flip-Flop The LSTTL / MSI SN74LS174 is a high speed Hex D Flip-Flop.

The device is used primarily as a 6-bit edge-triggered storage register.

The information on the D inputs is transferred to storage during the LOW to HIGH clock transition.

The device has a Master Reset to simultaneously clear all flip-flops.

The LS174 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families.

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74LS174 Features

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