Description
The NM24C03 C05 C09 C17 devices are 2048 4096 8192 16 834 bits respectively of CMOS non-volatile electrically erasable memory These devices conform to all specifications in the I2C 2-wire protocol and are designed to minimize device pin count and simplify PC board layout requirements
The upper half of the memory can be disabled (Write Protected) by connecting the WP pin to VCC This section of memory then becomes unalterable unless WP is switched to VSS
This communication protocol uses CLOCK (SCL
