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LM2507 - Display interface Serializer/Deserializer

Description

The LM2507 device adapts i80 CPU style display interfaces to the Mobile Pixel Link (MPL) Level zero serial link.

When using smart CPU type interfaces, two chip selects support a main and sub display.

Features

  • n CPU Display Interface support up to 800 x 300 1⁄2SVGA formats n Dual displays supported.
  • CS1.
  • & CS2.
  • n MPL-Level 0 Physical Layer using two data and one clock signal n Low Power Consumption n Pinout mirroring enables straight through layout with minimal vias n Level translation between host and display n Link power down mode reduces quiescent power under < 10 µA n 1.74V to 2.0V core / analog supply voltage range n 1.74V to 3.0V I/O supply voltage range System Benefits n n n n.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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LM2507 Low Power Mobile Pixel Link (MPL) Level 0, 16-bit CPU Display interface Serializer and Deserializer August 2006 LM2507 Low Power Mobile Pixel Link (MPL) Level 0, 16-bit CPU Display interface Serializer and Deserializer General Description The LM2507 device adapts i80 CPU style display interfaces to the Mobile Pixel Link (MPL) Level zero serial link. When using smart CPU type interfaces, two chip selects support a main and sub display. A mode pin configures the device as a Master (MST) or Slave (SLV) so the same chip can be used on both sides of the interface. The interconnect is reduced from 21 signals to only 3 active signals with the LM2507 chipset easing flex interconnect design, size constraints and cost.
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