DS99R104 - (DS99R103 / DS99R104) DC-Balanced 24-Bit LVDS Serializer and Deserializer

Description

The DS99R103/104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.

Features

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• 3 MHz.
• 40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions.
• Capable to drive shielded twisted-pair cable.
• User selectable clock edge for parallel data on both Transmitter and Receiver coupling interface with no external coding required Individual power-down controls for both Transmitter and Receiver Embedded clock CDR (clock and data recovery) on Receiver and no external source of reference clock needed All codes RDL (random da.