CLC031A Datasheet (National Semiconductor) - SMPTE 292M/259M Digital Video Deserializer / Descrambler

CLC031A, SMPTE 292M/259M Digital Video Deserializer / Descrambler

The CLC031A SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate c

CLC031A Features

* a variabledepth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse L