Description
The CLC031 SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancilliary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate clock.
Features
- a variabledepth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancilliary data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented. The unique multi-functional I/O port of the CLC031 provides external access to functions and data stored in the configuration and control registers. This feature all.
CLC031_NationalSemiconductor.pdf
