ADC14V155 Datasheet PDF - National Semiconductor 14-Bit Bandwidth A/D Converter Specs

ADC14V155 - 14-Bit Bandwidth A/D Converter

Datasheet Summary

Description

The ADC14V155 is a high-performance CMOS analog-todigital converter with LVDS outputs.

It is capable of converting analog input signals into 14-Bit digital words at rates up to 155 Mega Samples Per Second (MSPS).

Features

1.1 GHz Full Power Bandwidth.
Internal sample-and-hold circuit.
Low power consumption.
Internal precision 1.0V reference.
Single-ended or Differential clock modes.
Clock Duty Cycle Stabilizer.
Dual +3.3V and +1.8V supply operation.
Power-down and Sleep modes.
Offset binary or 2's complement output data format.
Dual Data Rate (DDR) LVDS outputs.
Pin-compatible: ADC12V170.
48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch) Key Specificati.

Datasheet Details

Part number	ADC14V155
Manufacturer	National Semiconductor
File Size	371.84 KB
Description	14-Bit Bandwidth A/D Converter
Datasheet	ADC14V155 Datasheet
Additional preview pages of the ADC14V155 datasheet.

📁 Similar Datasheet

ADC14V155 - 1.1GHz Bandwidth A/D Converter (Texas Instruments)

ADC14061 - A/D Converter (Texas Instruments)

ADC1410S - Single 14-bit ADC (NXP Semiconductors)

ADC1412D065 - Dual 14-bit ADC (NXP Semiconductors)

ADC1412D080 - Dual 14-bit ADC (NXP Semiconductors)

ADC1412D105 - Dual 14-bit ADC (NXP Semiconductors)

ADC1412D125 - Dual 14-bit ADC (NXP Semiconductors)

ADC1413D - Dual 14-bit ADC (NXP Semiconductors)

ADC1413D065 - Dual 14-bits ADC (NXP Semiconductors)

ADC1413D080 - Dual 14-bits ADC (NXP Semiconductors)

Full PDF Text Transcription

Click to expand full text

ADC14V155 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs ADC14V155 April 28, 2009 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs General Description The ADC14V155 is a high-performance CMOS analog-todigital converter with LVDS outputs. It is capable of converting analog input signals into 14-Bit digital words at rates up to 155 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data rate) format; this allows both edges of the output clock to be utilized while achieving a smaller package size. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance.

Published: Apr 25, 2007 |