P5020 - QorIQ integrated communication processor

Datasheet Details

Part number	P5020
Manufacturer	NXP
File Size	3.19 MB
Description	QorIQ integrated communication processor
Datasheet	P5020-NXP.pdf

Two e5500 Power Architecture cores (one on the P5010).
Each core has a backside 512-Kbyte L2 Cache with ECC.
Three levels of instructions: User, Supervisor, and Hypervisor.
Independent boot and reset.
Secure boot capability.
CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet endpoints.
2-Mbyte CoreNet platform cache with ECC (one on the P5010).
One 10-Gigabit Ethernet (XAUI) controller.

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Published: Sep 13, 2024 |