74AUP2G80 Low-power dual D-type flip-flop

NXP

Description

www.DataSheet4U.com 74AUP2G80 Low-power dual D-type ﬂip-ﬂop; positive-edge trigger Rev.01 * 25 August 2006 Product data sheet 1.General de.
The 74AUP2G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

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Datasheet Specifications

Part number: 74AUP2G80
Manufacturer: NXP ↗
File Size: 120.50 KB
Datasheet: 74AUP2G80_PhilipsSemiconductors.pdf
Description: Low-power dual D-type flip-flop

Features

* s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-D Class 3A exceeds 500

Applications

* using IOFF. The IOFF circuitry disables the output, preventing the damaging backﬂow current through the device when it is powered down. The 74AUP2G80 provides the single positive-edge triggered D-type ﬂip-ﬂop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition

74AUP2G80 Distributors

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74AUP2G80 Low-power dual D-type flip-flop NXP

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