74AUP1G17 Low-power Schmitt-trigger buffer

NXP

Description

www.DataSheet4U.com 74AUP1G17 Low-power Schmitt-trigger buffer Rev.01 * 26 July 2005 Product data sheet 1.General .
The 74AUP1G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

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Datasheet Specifications

Part number: 74AUP1G17
Manufacturer: NXP ↗
File Size: 122.60 KB
Datasheet: 74AUP1G17_PhilipsSemiconductors.pdf
Description: Low-power Schmitt-trigger buffer

Features

* s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-C exceeds 2000 V x MM

Applications

* using IOFF. The IOFF circuitry disables the output, preventing the damaging backﬂow current through the device when it is powered down. The 74AUP1G17 provides the single Schmitt-trigger buffer. It is capable of transforming slowly changing input signals into sharply deﬁned, jitter-free output signal

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74AUP1G17 Low-power Schmitt-trigger buffer NXP

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