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74AHCT273 Octal D-type flip-flop

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Description

INTEGRATED CIRCUITS DATA SHEET 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger Product specification File under Integrat.
74AHC273; 74AHCT273 The 74AHC/AHCT273 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).

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Features

* Ideal buffer for MOS microcontroller or memory
* Common clock and master reset
* ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V
* Balanced propagation delays
* All inputs have Schmit

Applications

* where the true output only is required and the clock and master reset are common to all storage elements. TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay CP to Qn MR to Qn fmax CI CO CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL ×

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