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D45128841G5 - UPD45128841G5

Description

The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.

Features

  • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge.
  • Pulsed interface.
  • Possible to assert random column address in every cycle.
  • Quad internal banks controlled by BA0(A13) and BA1(A12).
  • Byte control (×16) by LDQM and UDQM.
  • Programmable Wrap sequence (Sequential / Interleave).
  • Programmable burst length (1, 2, 4, 8 and full page).
  • Programmable /CAS latency (2 and 3).
  • Automatic precharge.

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Datasheet Details

Part number D45128841G5
Manufacturer NEC
File Size 855.93 KB
Description UPD45128841G5
Datasheet download datasheet D45128841G5 Datasheet
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Full PDF Text Transcription

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www.DataSheet4U.com DATA SHEET MOS INTEGRATED CIRCUIT µPD45128441, 45128841, 45128163 128M-bit Synchronous DRAM 4-bank, LVTTL Description The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL). These products are packaged in 54-pin TSOP (II).
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