MC100LVELT23 Datasheet - Motorola

MC100LVELT23 DUAL DIFFERENTIAL LVPECL/LVDS TO LVTTL TRANSLATOR

D0 1 8 VCC PIN Qn Dn VCC GND FUNCTION TTL Outputs Diff LVPECL Inputs +3.3V Supply Ground D0 2 LVPECL TTL 7 Q0 D1 3 6 Q1 D1 4 5 GND Figure 1. 8 *Lead Pinout and Logic Diagram 8/99 © Motorola, Inc. 1999 3 *1 REV 1.0 MC100LVELT23 MAXIMUM RATINGS * Symbol VCC TA T.

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC100LVELT23/D Dual Differential LVPECL to TTL Translator The MC100LVELT23 is a dual differential LVPECL to TTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the LVELT23 makes it ideal for applications which require the translation of a clock and a data signal. The LVELT23 is available in only the ECL 100K standard. Sinc.

MC100LVELT23 Datasheet (70.57 KB)