Description
Reset, Clocking, and Initialization Part II
e500 Core Complex and L2 Cache Core Complex Overview Core Register Summary L2 Look-Aside Cache/SRAM Part III
Memory, Security, and I/O Interfaces e500 Coherency Module DDR Memory Controller Programmable Interrupt Controller I2C Interface DUART Local Bus Controller Three-Speed Ethernet Controllers DMA Controller PCI Bus Interface Security Engine (SEC) 2.0 Part IV
Global Functions and Debug Global Utilities Performance Monitor De
Features
- and Watchpoint Facility
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DataSheet 4 U . com
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Part I.
 
- Overview Overview Memory Map Signal.