SN54LS165 Datasheet - Motorola Inc

SN54LS165 8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER

The SN54/74LS165 contains eight clocked master/slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. Parallel data enters when the PL signal is LOW. The parallel data can change while PL is LOW, provided that the recommended setup.

8-BIT PARALLEL-TO-SERIAL SHIFT REGISTER The SN54 / 74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputing occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new data enters via the Serial Data (DS) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable. SN54/74.

SN54LS165 Features

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