M2V56S30TP - 256M Synchronous DRAM

Product Overview

Mitsubishi

Datasheet Details

Part number	M2V56S30TP
Manufacturer	Mitsubishi
File Size	244.10 KB
Description	256M Synchronous DRAM
Datasheet	M2V56S30TP Datasheet
Additional preview pages of the M2V56S30TP datasheet.

Product details

Description

M2V56S20TP is a 4-bank x 16777216-word x 4-bit, M2V56S30TP is a 4-bank x 8388608-word x 8-bit, M2V56S40TP is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface.

Features

- Single 3.3v±0.3V power supply - Max. Clock frequency 100MHz(-7/-8), 133MHz (-6) - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/full page (programmable) - Burst type- sequential / interleave (programmable) - Random column access - Auto precharge / All bank precharge controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto.

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Published: May 2, 2005 |