M2S56D30TP - 256M Double Data Rate Synchronous DRAM

Product Overview

Mitsubishi

Datasheet Details

Part number	M2S56D30TP
Manufacturer	Mitsubishi
File Size	259.90 KB
Description	256M Double Data Rate Synchronous DRAM
Datasheet	M2S56D30TP Datasheet
Additional preview pages of the M2S56D30TP datasheet.

Product details

Description

M2S56D20TP is a 4-bank x 16777216-word x 4-bit, M2S56D30TP is a 4-bank x 8388608-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface.

Features

- Vdd=Vddq=2.5v±0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 1.5/2.0/2.5 (programmable) - Burst length- 2/4/8 (program.

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Published: May 2, 2005 |