Datasheet Specifications
- Part number
- M2S56D20ATP
- Manufacturer
- Mitsubishi
- File Size
- 815.69 KB
- Datasheet
- M2S56D20ATP-Mitsubishi.pdf
- Description
- 256M Double Data Rate Synchronous DRAM
Description
DDR SDRAM (Rev.1.2) Jun.'01 Preliminary MITSUBISHI LSIs M2S56D20/ 30/ 40ATP 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are.
Features
* - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each poM2S56D20ATP Distributors
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