MT4LC1M16E5 - EDO DRAM

Micron Technology

Datasheet Details

Part number	MT4LC1M16E5
Manufacturer	Micron Technology
File Size	385.15 KB
Description	EDO DRAM
Datasheet	MT4LC1M16E5_MicronTechnology.pdf

The 1 Meg x 16 is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x16 configuration.

JEDEC- and industry-standard x16 timing, functions, pinouts, and packages.
High-performance CMOS silicon-gate process.
Single power supply (+3.3V ±0.3V or 5V ±10%).
All inputs, outputs and clocks are TTL-compatible.
Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR), HIDDEN; optional self refresh (S).
BYTE WRITE access cycles.
1,024-cycle refresh (10 row, 10 column addresses).
Extended Data-Out (EDO) PAGE MODE access.

📁 MT4LC1M16E5 Similar Datasheet

Other Datasheets by Micron Technology

Published: Jan 16, 2006 |