CD4027BMS Datasheet (Intersil Corporation) - CMOS Dual J-K Master-Slave Flip-Flop

CD4027BMS, CMOS Dual J-K Master-Slave Flip-Flop

of ‘B’ Series CMOS Devices” Q2 1 Q2 2 CLOCK 2 3 RESET 2 4 K2 5 J2 6 SET 2 7 VSS 8 16 VDD 15 Q1 14 Q1 13 CLOCK 1 12 RESET 1 11 K1 10 J1 9 SET 1 Functional Diagram SET 1 9 VDD 16 J1 10 K1 11 CLOCK1 13 F/F1 15 Q1 14 Q1 Applications * Registers, Counters, Control Circuits RESET1 12 SET2 J2

CD4027BMS Features

* High Voltage Type (20V Rating)

* Set - Reset Capability

* Static Flip-Flop Operation - Retains State Indeﬁnitely with Clock Level Either “High” or “Low”

* Medium Speed Operation - 16MHz (typ.) Clock Toggle Rate at 10V

* Standardized Symmetrical Output Charac