IS61DDPB24M18 DDR-IIP (Burst of 2) CIO Synchronous SRAMs

Integrated Silicon Solution

Description

72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burs.t of 2) CIO Synchronous SRAMs (2.5 Cycle Read Latency) Advanced Information May 2009 .
The 72Mb IS61DDPB22M36 and IS61DDPB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

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Datasheet Specifications

Part number: IS61DDPB24M18
Manufacturer: Integrated Silicon Solution
File Size: 572.22 KB
Datasheet: IS61DDPB24M18-IntegratedSiliconSolution.pdf
Description: DDR-IIP (Burst of 2) CIO Synchronous SRAMs

Features

* 2M x 36 or 4M x 18.
* On-chip delay-locked loop (DLL) for wide data valid window.
* Common data input/output bus.
* Synchronous pipeline read with self-timed late write operation.
* Double data rate (DDR-IIP) interface for read and write input ports.

IS61DDPB24M18 Distributors

📁 Related Datasheet

IS61DDPB24M18C IS61DDPB24M18C1 IS61DDPB24M18C2 IS61DDPB22M36C IS61DDPB22M36C1 IS61DDPB22M36C2

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IS61DDPB24M18 DDR-IIP Burst CIO Synchronous SRAMs Integrated Silicon Solution

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