Description
IS61DDPB24M18C/C1/C2 IS61DDPB22M36C/C1/C2 4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Latency) APRIL 2018 .
at page 6 for each ODT option.
Features
* 2Mx36 and 4Mx18 configuration available.
* Common I/O read and write ports.
* Max. 567 MHz clock for high bandwidth
* Synchronous pipeline read with self-timed late write
operation.
* Double Data Rate (DDR) interface for read and
write input ports.
* 2.5 cycle read latency.
Applications
* where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance
