Description
72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burs.t of 2) CIO Synchronous SRAMs (2.5 Cycle Read Latency) Advanced Information May 2009 .
The 72Mb IS61DDPB22M36 and IS61DDPB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.
Features
* 2M x 36 or 4M x 18.
* On-chip delay-locked loop (DLL) for wide data valid window.
* Common data input/output bus.
* Synchronous pipeline read with self-timed late
write operation.
* Double data rate (DDR-IIP) interface for read and write input ports.
