IDT54FCT388915T Datasheet - Integrated Device Technology

IDT54FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE)

RST is low, all the outputs are put in high impedance state and The IDT54/74FCT388915T uses phase-lock loop technol- registers at Q, Q and Q/2 outputs are reset. ogy to lock the frequency and phase of outputs to the input The IDT54/74FCT388915T requires one external loop filter reference clock. It .

IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES Integrated Device Technology, Inc. 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) IDT54/74FCT388915T 70/100/133/150 PRELIMINARY is fed back to the PLL at the FEEDBACK input resulting in essentially zero delay across the device. The PLL consists of 0.5 MICRON CMOS Technology the phase/frequency detector, charge pump, loop filter and Input frequency r.

IDT54FCT388915T Features

* FUNCTIONAL BLOCK DIAGRAM FEEDBACK Phase/Freq. Detector Voltage Controlled Oscilator LF REF_SEL PLL_EN 0 1 Mux 2Q (÷ 1) (÷ 2) 1M u x 0 D Q LOCK 0M u 1x Charge Pump SYNC (0) SYNC (1) Q0 Q1 Divide -By-2 FREQ_SEL OE/RST CP R Q D CP R D CP R D CP D CP D CP D CP R 3052 drw 01 R R R Q Q Q2 Q Q3

IDT54FCT388915T_IntegratedDeviceTechnology.pdf