Description
Integrated Circuit Systems, Inc.Preliminary Information M1040 VCSO BASED CLOCK PLL WITH AUTOSWITCH PIN ASSIGNMENT (9 x 9 mm SMT) MR_SEL2 GND AUTO .
Features
* dual differential inputs with two modes of input selection: manual and automatic upon clock failure. The clock multiplication ratios and output divider ratio are pin selectable. This device provides two outputs. External loop components allow the tailoring of PLL loop response. FEATURESApplications
* to assure PLL tracking, especially during GR-253 jitter tolerance testing. The recommended maximum phase detector frequency for loop timing mode is 19.44MHz. The LOL pin should not be used during loop timing mode. When LOL is to be used for system health monitoring, the phase detector frequency shouM1040 Distributors
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