IS61QDP2B22M18A2 Datasheet PDF (36Mb QUADP (Burst 2) Synchronous SRAM)

IS61QDP2B22M18A2 - 36Mb QUADP (Burst 2) Synchronous SRAM

This page provides the datasheet information for the IS61QDP2B22M18A2, a member of the IS61QDP2B22M18A 36Mb QUADP (Burst 2) Synchronous SRAM family.

Description

devices.

need for high-speed bus turnaround.

operations are self-timed.

Features

1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.0 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and cont.

Datasheet Details

Part number	IS61QDP2B22M18A2
Manufacturer	ISSI (now Infineon)
File Size	660.37 KB
Description	36Mb QUADP (Burst 2) Synchronous SRAM
Datasheet	IS61QDP2B22M18A2 Datasheet
Additional preview pages of the IS61QDP2B22M18A2 datasheet.

📁 Similar Datasheet

IS61C1024 - 128K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C1024L - 128K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C256 - 32K x 8 Low Voltage CMOS STATIC RAM (Integrated Silicon Solution)

IS61C25616 - 256K x 8 High Speed CMOS STATIC RAM (Integrated Silicon Solution)

IS61C25616AL - 256K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C25616AS - 256K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C256AH - 32K x 8 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C256AL - 32K x 8 High Speed CMOS STATIC RAM (Integrated Silicon Solution)

IS61C3216AL - 32K x 16 HIGH-SPEED CMOS STATIC RAM (Integrated Silicon Solution)

IS61C512 - 64K x 8 High Speed CMOS Static RAM (Integrated Silicon Solution)

Full PDF Text Transcription

Click to expand full text

IS61QDP2B22M18A/A1/A2 IS61QDP2B21M36A/A1/A2 2Mx18, 1Mx36 36Mb QUADP (Burst 2) Synchronous SRAM (2.0 CYCLE READ LATENCY) JANUARY 2015 FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 Cycle read latency.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.

Published: Jun 10, 2016 |