IS61QDP2B22M18A - 36Mb QUADP (Burst 2) Synchronous SRAM

ISSI

IS61QDP2B22M18A Datasheet Preview — Preview of IS61QDP2B22M18A PDF

Datasheet Details

Part number	IS61QDP2B22M18A
Manufacturer	ISSI
File Size	660.37 KB
Description	36Mb QUADP (Burst 2) Synchronous SRAM
Datasheet	IS61QDP2B22M18A-ISSI.pdf

IS61QDP2B22M18A Product details

Description

The and are synchronous, high- performance CMOS static random access memory (SRAM) devices.These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.Refer to the for a description of the basic operations of these SRAMs.Read and write addresses are registered on alternating rising edges of the K clock.Read and write performed in double data rate.The

Features

1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.0 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and cont.

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Published: Jun 10, 2016 |