HY5S6B6, HY5S6B6D Datasheet - Hynix Semiconductor

HY5S6B6 (HY5S6B6D/L/S/F/P) 4Banks x 1M x 16-Bits SDRAM

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.3 / July 2004 1 w w w .D at h S a t e e 4U . m o c HY5S6B6D(L/S)F(P)-xE 4Banks x1M x 16bits Synchronous DRAM DESCRIPTION The Hynix Low Pow.

Document Title 4Bank x 1M x 16bits Synchronous DRAM Revision History w w w Revision No. 0.1 0.2 0.3 Initial Draft .D at h S a t e e 4U . m o c HY5S6B6D(L/S)F(P)-xE 4Banks x1M x 16bits Synchronous DRAM History Draft Date Sep. 2003 Oct. 2003 Nov. 2003 July 2004 Remark Preliminary Preliminary Append Super-Low Power Group to the Data-sheet Changed DC Characteristics Changed Package Information w w w .D t a S a e h t e U 4 .c m o This document is a general product descri.

HY5S6B6 Features

* Standard SDRAM Protocol Internal 4bank operation

* Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage interface to reduce I/O power Low Power Features - PASR(Partial Array Self Refresh) - AUTO TCSR (Temperature Compensated Self Refresh) - DS (Drive Streng

HY5S6B6D_HynixSemiconductor.pdf