HY5DU28822LT, HY5DU28822AT - 3rd 128M DDR SDRAM

Hynix Semiconductor

Datasheet Details

Part number	HY5DU28822LT, HY5DU28822AT
Manufacturer	Hynix Semiconductor
File Size	376.76 KB
Description	3rd 128M DDR SDRAM
Datasheet	HY5DU28822AT_HynixSemiconductor.pdf
Note	This datasheet PDF includes multiple part numbers: HY5DU28822LT, HY5DU28822AT. Please refer to the document for exact specifications by model.

and is subject to change without notice.

VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both ri.

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Published: Mar 24, 2006 |