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HY5DU281622AT-6 128M(8Mx16) DDR SDRAM

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Description

HY5DU281622AT-6 128M(8Mx16) DDR SDRAM HY5DU281622AT This document is a general product .
and is subject to change without notice.

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Features

* VDD, VDDQ = 2.5V +/- 5% All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface

Applications

* which requires high bandwidth. The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks

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