Description
www.DataSheet4U.net 256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O Specification of 256Mb (8Mx32bit) Mobile DDR SDRAM Memory Cell Array - Org.
and is subject to change without notice.
Features
* SUMMARY
* Mobile DDR SDRAM
clock cycle
* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM)
- Double data rate architecture: two data transfer per
* Mobile DDR SDRAM INTERFACE
- x32 bus width - Multiple
Applications
* which use the battery such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of 2,097,152 x32. The HYNIX H5MS262(53)2JFR series uses a double-data-rate architecture to achieve high-speed operation. The doubl
